Semiconductor memory device

A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The...

Full description

Saved in:
Bibliographic Details
Main Authors Yoneya, Kazuhide, Kudou, Manami, Koyanagi, Masaru, Hisada, Toshiki, Matsudera, Katsuki
Format Patent
LanguageEnglish
Published 28.03.2002
Online AccessGet full text

Cover

Loading…
Abstract A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.
AbstractList A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.
Author Hisada, Toshiki
Kudou, Manami
Yoneya, Kazuhide
Matsudera, Katsuki
Koyanagi, Masaru
Author_xml – sequence: 1
  givenname: Kazuhide
  surname: Yoneya
  fullname: Yoneya, Kazuhide
– sequence: 1
  givenname: Manami
  surname: Kudou
  fullname: Kudou, Manami
– sequence: 2
  givenname: Masaru
  surname: Koyanagi
  fullname: Koyanagi, Masaru
– sequence: 3
  givenname: Toshiki
  surname: Hisada
  fullname: Hisada, Toshiki
– sequence: 4
  givenname: Katsuki
  surname: Matsudera
  fullname: Matsudera, Katsuki
BookMark eNrjYmDJy89L5WSQDk7NzUzOz0spTS7JL1LITc3NL6pUSEkty0xO5WFgTUvMKU7lhdLcDJpuriHOHrqlxQWJJal5JcXxiQUFOZnJiSWZ-XnF8UYGBkBkbGZpZGFMiloAXCgseA
ContentType Patent
DBID EFI
DatabaseName USPTO Published Applications
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EFI
  name: USPTO Published Applications
  url: http://www.uspto.gov/patft/index.html
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
ExternalDocumentID 20020036928
GroupedDBID EFI
ID FETCH-uspatents_applications_200200369283
IEDL.DBID EFI
IngestDate Sun Mar 05 22:09:52 EST 2023
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-uspatents_applications_200200369283
OpenAccessLink https://patentcenter.uspto.gov/applications/09963805
ParticipantIDs uspatents_applications_20020036928
PublicationCentury 2000
PublicationDate 20020328
PublicationDateYYYYMMDD 2002-03-28
PublicationDate_xml – month: 03
  year: 2002
  text: 20020328
  day: 28
PublicationDecade 2000
PublicationYear 2002
Score 2.5535128
Snippet A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group...
SourceID uspatents
SourceType Open Access Repository
Title Semiconductor memory device
URI https://patentcenter.uspto.gov/applications/09963805
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQsUhLTgHWy8bAGEiz0DUxNUrRtTQ3SNJNMUo0NTQ2TE2yNAHtHfb1M_MINfGKMI2AbgoD7YUpALaw8kpACxNTi_RKiwtK8sGrK1Fmc4GNGmCqAR1cymxhDm4sunlyM3ACVYM1FyNVEG6CDGwBYFEhBqbUPBEG6WDQmvP8PNBhqvlFCrmg5ayVCimpoGwpyqDp5hri7KELNyke2V7QjY2gpVxmlsAqWYyBBdg9T5VgAOoFNmGSjFOALRlgXzMl2cLYJA3YJjCwSDFLS7NIM5dkUCJsnhQxiqQZuMB3kRgAQ9ZChoGlpKg0VRZYJZYkyYHDAADXQ2rY
link.rule.ids 230,309,786,879,891,64416
linkProvider USPTO
linkToPdf http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQsUhLTgHWy8bAGEiz0DUxNUrRtTQ3SNJNMUo0NTQ2TE2yNAHtHfb1M_MINfGKMI2Abo8G74XJBWYj3QKgW4r1SosLSvLBiyuBxTsk4nUhhz-DzgjMA50-UJ6Xk5-YEpCSpg9abAA6XMXSyIKZgRVUy4PSu6ubJzcDJ9AgYMMtr6QYqepwE2RgCwCLCjEwpeaJMEgHg1aj5-eBjlnNL1LIBS10rVRISQVlWFEGTTfXEGcPXbhJ8cjzy_FIlhuLMbAAO-6pEgxAvcDGTZJxCrCNA-yFpiRbGJukAVsLBhYpZmlpFmnmkgxKhM2TIkaRPANHgItbvI-nn7c0Axf4whIDYPBbyDCwlBSVpsoC682SJDlwcAAA0cJ2CQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Semiconductor+memory+device&rft.inventor=Yoneya%2C+Kazuhide&rft.inventor=Kudou%2C+Manami&rft.inventor=Koyanagi%2C+Masaru&rft.inventor=Hisada%2C+Toshiki&rft.inventor=Matsudera%2C+Katsuki&rft.date=2002-03-28&rft.externalDBID=n%2Fa&rft.externalDocID=20020036928