Semiconductor memory device

A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The...

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Bibliographic Details
Main Authors Yoneya, Kazuhide, Kudou, Manami, Koyanagi, Masaru, Hisada, Toshiki, Matsudera, Katsuki
Format Patent
LanguageEnglish
Published 28.03.2002
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Summary:A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.