A 56-nm CMOS 99-mm super(2) 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 1
• Main Authors: Takeuchi, K, Kameda, Y, Fujimura, S, Otake, H, Hosono, K, Shiga, H, Watanabe, Y, Futatsuyama, T, Shindo, Y, Kojima, M, Iwai, M, Shirakawa, M, Ichige, M, Hatakeyama, K, Tanaka, S, Kamei, T, Fu, J-Y, Cernea, A, Li, Y, Higashitani, M, Hemink, G, Sato, S, Oowada, K, Lee, S-C, Hayashida, N, Wan, J, Lutze, J, Tsao, S, Mofidi, M, Sakurai, K, Tokiwa, N, Waki, H, Nozawa, Y, Kanazawa, K, Ohshima, S
• Format: Journal Article
• Language: English
• Published: 01.01.2007
• Subjects: Blocking; Chips; Circuits; CMOS; Flash memory (computers); Programming; Semiconductors
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2006.888299

A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm super(2), has been successfully developed. This is the world's first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum super(2) per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size