A MULTI-OBJECTIVE PERSPECTIVE FOR OPERATOR SCHEDULING USING FINE-GRAINED DVS ARCHITECTURES

The stringent power budget of fine grained power managed digital integrated circuits has driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates the authors to revisit the classical oper...

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Published inInternational journal of VLSI design & communication systems Vol. 4; no. 1; p. 105
Main Authors Mukherjee, Rajdeep, Ghosh, Priyankar, Dasgupta, Pallab, Pal, Ajit
Format Journal Article
LanguageEnglish
Published 01.02.2013
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Abstract The stringent power budget of fine grained power managed digital integrated circuits has driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates the authors to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. They study the design space defined due to this trade-off and present a branch-and-bound algorithm to explore this state space and report the pareto-optimal front with respect to area and power. The scheduling also aims at maximum resource sharing and is able to attain sufficient area and power gains for complex benchmarks, when timing constraints are relaxed by sufficient amount. Experimental results show that the algorithm that operates without any user constraint (area/power) is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.
AbstractList The stringent power budget of fine grained power managed digital integrated circuits has driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates the authors to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. They study the design space defined due to this trade-off and present a branch-and-bound algorithm to explore this state space and report the pareto-optimal front with respect to area and power. The scheduling also aims at maximum resource sharing and is able to attain sufficient area and power gains for complex benchmarks, when timing constraints are relaxed by sufficient amount. Experimental results show that the algorithm that operates without any user constraint (area/power) is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.
Author Mukherjee, Rajdeep
Ghosh, Priyankar
Dasgupta, Pallab
Pal, Ajit
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Snippet The stringent power budget of fine grained power managed digital integrated circuits has driven chip designers to optimize power at the cost of area and delay,...
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StartPage 105
SubjectTerms Algorithms
Benchmarks
Budgeting
Design engineering
Integrated circuits
Operators
Scheduling
Tradeoffs
Title A MULTI-OBJECTIVE PERSPECTIVE FOR OPERATOR SCHEDULING USING FINE-GRAINED DVS ARCHITECTURES
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