Higher Order FIR Filter Architecture Design Using Optimized Booth Multipliers and SRCSLA Adders with Retiming for Denoising of ECG Signals

In this paper, a power and delay efficient higher order filter architecture is designed and implemented for the ECG signal processing applications. To reduce the critical path delay, the retiming is introduced in the direct form FIR architecture. The optimized multipliers and adders are key blocks i...

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Bibliographic Details
Published inInternational journal of communication networks and information security Vol. 16; no. 4; pp. 105 - 119
Main Authors Bhadavath, Kiran Kumar, Livinsa, Z Mary
Format Journal Article
LanguageEnglish
Published Kohat Kohat University of Science and Technology (KUST) 01.12.2024
Subjects
Adding circuits
Complexity
Critical path
Delay
Design
Energy efficiency
FIR filters
Literature reviews
Multipliers
Power consumption
Signal processing
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Summary:In this paper, a power and delay efficient higher order filter architecture is designed and implemented for the ECG signal processing applications. To reduce the critical path delay, the retiming is introduced in the direct form FIR architecture. The optimized multipliers and adders are key blocks in the filter architecture to increase the delay and power consumption. In this regard, an optimized Radix-4 Booth multiplier is designed using a modified booth encoder and selector blocks along with the proposed improved version of Square Root Carry Select Adders (SRCSLA). The design metrics of the multiplier, which is used to multiply the filter coefficients and input samples also improved by using the proposed SRCSLA. For the proposed SRCSLA, The Carry Look Ahead and Carry Skip Adder concepts are combined and modified according to the proposed SRCSLA. Different bit size-based SRCSLA adders are implemented for the proposed multiplier architecture and to sum the final filter output. The adder structure speed is improved by modified carry-producing and propagating blocks. The retiming-based direct-form FIR filter architecture for the order N = 32 is coded by HDL and synthesized using Genus tools from Cadence in 45nm CMOS technology. Area complexity, time complexity, and power consumption are estimated by the reports generated by the Genus synthesis tool. The trade-off design metrics Area-Delay-Product (ADP) and Power-Delay-Product (PDP) are also estimated and compared with the conventional filter architectures, and existing filter distributed system architectures.
ISSN:2073-607X
2076-0930