PIUMA: Programmable Integrated Unified Memory Architecture

• Published in: arXiv.org
• Main Authors: Aananthakrishnan, Sriram, Ahmed, Nesreen K, Cave, Vincent, Cintra, Marcelo, Demir, Yigit, Kristof Du Bois, Eyerman, Stijn, Fryman, Joshua B, Ganev, Ivan, Heirman, Wim, Hoppe, Hans-Christian, Howard, Jason, Hur, Ibrahim, Kodiyath, MidhunChandra, Jain, Samkit, Klowden, Daniel S, Landowski, Marek M, Montigny, Laurent, More, Ankit, Ossowski, Przemyslaw, Pawlowski, Robert, Pepperling, Nick, Petrini, Fabrizio, Sikora, Mariusz, Balasubramanian Seshasayee, Smith, Shaden, Szkoda, Sebastian, Tayal, Sanjaya, Jesmin Jahan Tithi, Vandriessche, Yves, Wrosz, Izajasz P
• Format: Paper
• Language: English
• Published: Ithaca Cornell University Library, arXiv.org 13.10.2020
• Subjects: Computer architecture; Microprocessors

High performance large scale graph analytics is essential to timely analyze relationships in big data sets. Conventional processor architectures suffer from inefficient resource usage and bad scaling on graph workloads. To enable efficient and scalable graph analysis, Intel developed the Programmable Integrated Unified Memory Architecture (PIUMA). PIUMA consists of many multi-threaded cores, fine-grained memory and network accesses, a globally shared address space and powerful offload engines. This paper presents the PIUMA architecture, and provides initial performance estimations, projecting that a PIUMA node will outperform a conventional compute node by one to two orders of magnitude. Furthermore, PIUMA continues to scale across multiple nodes, which is a challenge in conventional multinode setups.