A Range-Scaled 13b 100 MS/s 0.13 um CMOS SHA-Free ADC Based on a Single Reference

• Published in: Journal of semiconductor technology and science Vol. 13; no. 2; pp. 98 - 107
• Main Authors: Hwang, Dong-Hyun, Song, Jung-Eun, Nam, Sang-Pil, Kim, Hyo-Jin, An, Tai-Ji, Kim, Kwang-Soo, Lee, Seung-Hoon
• Format: Journal Article
• Language: Korean
• Published: 2013
• Subjects: pipeline; range scaling; Analog-to-digital converter (ADC); two-step reference selection; SHA-free; high resolution
• ISSN: 1598-1657

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.