Charge sharing write driver and half-$V_{{\rm DD}}$VDD pre-charge 8T SRAM with virtual ground for low-power write and read operation

• Published in: IET circuits, devices & systems Vol. 12; no. 1; pp. 94 - 98
• Main Authors: Maroof, Naeem, Kong, Bai-Sun
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 01.01.2018
• Subjects: Research Article; pre-charge 8T SRAM; conventional 8T design; virtual ground; read BL pre-charge scheme; dynamic read power; WE signal assertion; rail-to-rail levels; low-power read operation; 8T design; conventional 6T design; low-power write-read operation; supply voltage; C8T design; RBL leakages; write bitline charge sharing write driver; leakage current compensation block; C6T design; driver circuits; write dynamic power dissipation; write enable signal assertion; single-ended 8T SRAM; write BL pair; SRAM chips; RBL pre-charge scheme; virtual ground rail; charge sharing; low-power electronics; BL CSWD; write power dissipation

A novel write bitline (BL) charge sharing write driver (CSWD) and a half-$V_{{\rm DD}}$VDD read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing....