An IDE for Reconfigurable Video Array Processor

• Published in: 2021 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC) pp. 121 - 126
• Main Authors: Yang, Rong, Xie, Xiaoyan, Chai, Miaomiao, Fang, Lin, He, Wanqi, Sun, Jingtao
• Format: Conference Proceeding
• Language: English
• Published: APSIPA 14.12.2021
• Subjects: Complexity theory; Hardware; Heuristic algorithms; HEVC; IDE; instruction groups; Out of order; Parallel processing; Reconfigurable Array Processor; Semantics; Software; static back slicing

Integrated development environment (IDE) is one of the key points to construct software ecological of reconfigurable array processor (RAP) chips. However, transplanting from conventional IDE is a daunting task, because of the complexity of high-level behavior description in front-end and special spa...