15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
Computing-in-memory (CIM) is an attractive approach for energy-efficient neural network (NN) processors, especially for low-power edge devices. Previous CIM chips [1] -[5] have demonstrated macro and system-level design enabling multi-bit operations and sparsity support. However, several challenges...
Saved in:
Published in | 2021 IEEE International Solid- State Circuits Conference (ISSCC) Vol. 64; pp. 238 - 240 |
---|---|
Main Authors | , , , , , , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
13.02.2021
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | Computing-in-memory (CIM) is an attractive approach for energy-efficient neural network (NN) processors, especially for low-power edge devices. Previous CIM chips [1] -[5] have demonstrated macro and system-level design enabling multi-bit operations and sparsity support. However, several challenges exist, as shown in Fig. 15.2.1. First, though a previously proposed block-wise sparsity strategy [5] can power off ADCs, zeros still contributed to storage requirements, and power gating was not applied to computing resources. Second, on-chip SRAM CIM macros are not large enough to hold all weights. Updating weights between computing operations leads to significant performance loss. Finally, the limited sensing margin incurs poor accuracy for large NN models on practical datasets, such as ImageNet. The precision and power of the ADCs should be optimized and adjusted. |
---|---|
AbstractList | Computing-in-memory (CIM) is an attractive approach for energy-efficient neural network (NN) processors, especially for low-power edge devices. Previous CIM chips [1] -[5] have demonstrated macro and system-level design enabling multi-bit operations and sparsity support. However, several challenges exist, as shown in Fig. 15.2.1. First, though a previously proposed block-wise sparsity strategy [5] can power off ADCs, zeros still contributed to storage requirements, and power gating was not applied to computing resources. Second, on-chip SRAM CIM macros are not large enough to hold all weights. Updating weights between computing operations leads to significant performance loss. Finally, the limited sensing margin incurs poor accuracy for large NN models on practical datasets, such as ImageNet. The precision and power of the ADCs should be optimized and adjusted. |
Author | Wang, Yipeng Liu, Jiaxin Feng, Xiaoyu He, Yifan Su, Jian-Wei Huang, Yuxuan Sun, Nan Chung, Yen-Lin Li, Xueqing Liu, Yongpan Chang, Meng-Fan Hung, Li-Yang Yang, Huazhong Wu, Ping-Chun Yuan, Zhe Zhan, Mingtao Yue, Jinshan |
Author_xml | – sequence: 1 givenname: Jinshan surname: Yue fullname: Yue, Jinshan organization: Tsinghua University,Beijing,China – sequence: 2 givenname: Xiaoyu surname: Feng fullname: Feng, Xiaoyu organization: Tsinghua University,Beijing,China – sequence: 3 givenname: Yifan surname: He fullname: He, Yifan organization: Tsinghua University,Beijing,China – sequence: 4 givenname: Yuxuan surname: Huang fullname: Huang, Yuxuan organization: Tsinghua University,Beijing,China – sequence: 5 givenname: Yipeng surname: Wang fullname: Wang, Yipeng organization: Pi2star Technology,Beijing,China – sequence: 6 givenname: Zhe surname: Yuan fullname: Yuan, Zhe organization: Tsinghua University,Beijing,China – sequence: 7 givenname: Mingtao surname: Zhan fullname: Zhan, Mingtao organization: Tsinghua University,Beijing,China – sequence: 8 givenname: Jiaxin surname: Liu fullname: Liu, Jiaxin organization: Tsinghua University,Beijing,China – sequence: 9 givenname: Jian-Wei surname: Su fullname: Su, Jian-Wei organization: National Tsing Hua University,Hsinchu,Taiwan – sequence: 10 givenname: Yen-Lin surname: Chung fullname: Chung, Yen-Lin organization: National Tsing Hua University,Hsinchu,Taiwan – sequence: 11 givenname: Ping-Chun surname: Wu fullname: Wu, Ping-Chun organization: National Tsing Hua University,Hsinchu,Taiwan – sequence: 12 givenname: Li-Yang surname: Hung fullname: Hung, Li-Yang organization: National Tsing Hua University,Hsinchu,Taiwan – sequence: 13 givenname: Meng-Fan surname: Chang fullname: Chang, Meng-Fan organization: National Tsing Hua University,Hsinchu,Taiwan – sequence: 14 givenname: Nan surname: Sun fullname: Sun, Nan organization: Tsinghua University,Beijing,China – sequence: 15 givenname: Xueqing surname: Li fullname: Li, Xueqing organization: Tsinghua University,Beijing,China – sequence: 16 givenname: Huazhong surname: Yang fullname: Yang, Huazhong organization: Tsinghua University,Beijing,China – sequence: 17 givenname: Yongpan surname: Liu fullname: Liu, Yongpan organization: Tsinghua University,Beijing,China |
BookMark | eNp9kMFKAzEQhqMo2KpP4MF5gWyTbLO7OdZFsYfWhVQKXkpoYxvbTUKSRfpWPqJd6dnT8M__MR_MEF1ZZzVCj5RklBIxmkpZ12NW0DxjhNFM5AUXvLpAQ1qyigo-FuUlGrC8LHBVkOIGDWP8IoRwUVQD9EN5xmACLCs5Tg6XPBOLt0aOllC71nfJ2C02Fs9068IR5nNoglvrGF0A2XnvQk-A1AlPTsu1UUnD08Gt93hpooYPHRzIvfG-x5TdQNNfbNwp1dMZfJu0A2na7pCU1a6LZ61Kxtk_fqnNdpfg3W9Ur7pD15_qEPX9ed6ih5fnRf2KjdZ65YNpVTiuzl_I_29_AbNrYuA |
ContentType | Conference Proceeding |
DBID | 6IE 6IH CBEJK RIE RIO |
DOI | 10.1109/ISSCC42613.2021.9365958 |
DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library Online IEEE Proceedings Order Plans (POP) 1998-present |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library Online url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Engineering |
EISBN | 1728195497 9781728195490 |
EISSN | 2376-8606 |
EndPage | 240 |
ExternalDocumentID | 9365958 |
Genre | orig-research |
GroupedDBID | 6IE 6IF 6IH 6IK 6IL 6IM 6IN AAJGR ABLEC ACGFS ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP IPLJI JC5 M43 OCL RIE RIL RIO RNS |
ID | FETCH-ieee_primary_93659583 |
IEDL.DBID | RIE |
IngestDate | Wed Jun 26 19:27:22 EDT 2024 |
IsPeerReviewed | false |
IsScholarly | true |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-ieee_primary_93659583 |
ParticipantIDs | ieee_primary_9365958 |
PublicationCentury | 2000 |
PublicationDate | 2021-Feb.-13 |
PublicationDateYYYYMMDD | 2021-02-13 |
PublicationDate_xml | – month: 02 year: 2021 text: 2021-Feb.-13 day: 13 |
PublicationDecade | 2020 |
PublicationTitle | 2021 IEEE International Solid- State Circuits Conference (ISSCC) |
PublicationTitleAbbrev | ISSCC |
PublicationYear | 2021 |
Publisher | IEEE |
Publisher_xml | – name: IEEE |
SSID | ssj0005968 |
Score | 4.381084 |
Snippet | Computing-in-memory (CIM) is an attractive approach for energy-efficient neural network (NN) processors, especially for low-power edge devices. Previous CIM... |
SourceID | ieee |
SourceType | Publisher |
StartPage | 238 |
SubjectTerms | Artificial neural networks Common Information Model (computing) Program processors Sensors Solid state circuits System-level design System-on-chip |
Title | 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating |
URI | https://ieeexplore.ieee.org/document/9365958 |
Volume | 64 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1Nb4JAEN1YT-2lH9q0tW3m0GMXYRGFY0tqtAmWBI2mF8PCaIwJaxQO7a_qT-wuoLaNh96ALLtsZsgww3tvCHngjOuh6gHIWwypdIqYhuhw-bpbth7OMGah4g57g3Zv1HqdWJMKedxxYRAxB5-hpg7zf_mxiDJVKms6plK_s4_Ika2zgqu1h3M4bbvEbxm60-wHgeuq9MCUOSAztPLWXz1U8hDSPSXedvECObLUspRr0ecfXcb_Pt0Zqe_JeuDvwtA5qWByQU5-6AzWyJdhaQyegGkdi6aCdizNGb75QXMMRVcHOYouEuop2O0HDAZQ8gfEGlTbT6GkBuYQYEq35kR4lmFwSceLDcI7rgUEy1zrYQ5hEoOvZvSFPHP7HqhiLwQLBV4MExTZplw294p8_Div0MJopdgWybxOGt2Xodujav_TVaGIMS23bl6SaiISvCJgSbMbXMZ-1o5aIUaOwRGdmSMzFM5MK74mtUMz3By-3CDHyooKLW2Yt6SarjO8kx8DKb_PveAbRt65eQ |
link.rule.ids | 310,311,786,790,795,796,802,23958,23959,25170,27956,55107 |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LT8JAEN4gHtSLDzAqPubg0S19UKBHbSSgtDYpBOKFdOlACElLoD3or_InurstoIaDt7bZ7nYz00xn-n3fEHLPdKYGogcgq-lIuVOENECL8dfdbKrBBEM9ENxhx623-7WXoTkskIcNFwYRJfgMFXEo_-WH8TgVpbKqZQj1u-Ye2edxXm1kbK0toMOqN3MEl6Za1Y7v27ZIEAyeBeqakt_8q4uKDCKtY-Ksl8-wI3MlTZgy_vyjzPjf5zsh5S1dD7xNIDolBYzOyNEPpcES-dJMRYdH0JWGSZOYNkzF6r15fnUAWV8HPorOIuoI4O0HuC7kDIJ4CaLxZyzEBqbgY0LXBkV44oFwTgezFcI7LmPw51LtYQpBFIInZvRifmZ3HBDlXvBnAr4YRBinq3xZ6Rdy_EDWaKG_EHyLaFomldZzz25Tsf_RItPEGOVbN85JMYojvCBgcsNrjEd_vT6uBTi2NIZoTSyeozDdMMNLUto1w9Xuy3fkoN1zuqNux32tkENhUYGd1oxrUkyWKd7wT4OE3UqP-AYy77zN |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=2021+IEEE+International+Solid-+State+Circuits+Conference+%28ISSCC%29&rft.atitle=15.2+A+2.75-to-75.9TOPS%2FW+Computing-in-Memory+NN+Processor+Supporting+Set-Associate+Block-Wise+Zero+Skipping+and+Ping-Pong+CIM+with+Simultaneous+Computation+and+Weight+Updating&rft.au=Yue%2C+Jinshan&rft.au=Feng%2C+Xiaoyu&rft.au=He%2C+Yifan&rft.au=Huang%2C+Yuxuan&rft.date=2021-02-13&rft.pub=IEEE&rft.eissn=2376-8606&rft.volume=64&rft.spage=238&rft.epage=240&rft_id=info:doi/10.1109%2FISSCC42613.2021.9365958&rft.externalDocID=9365958 |