Problems and solutions for downsizing CMOS below 0.1 /spl mu/m

• Published in: ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425) pp. 1 - 19
• Main Authors: Iwai, H., Ohmi, S.-I.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Artificial intelligence; Clocks; CMOS process; CMOS technology; Dielectric substrates; Frequency; Large scale integration; MOS devices; MOSFET circuits; Random access memory

Progress of MOS LSI has been achieved by continuous downsizing of its components. However, the downsizing of CMOS devices is now facing severe difficulties at the 0.1 /spl mu/m generation because of various expected limitations. In order to overcome the problems, introduction of new materials and de...