Analytical Model and Verification Algorithm to Prevent Injection Induced Latchup Failures

Unexpected latchup qualification test failures of HV analog integrated circuit were observed and explained by a new mechanism - injection current upset of internal HV blocks resulting in overload and burnout of LV circuits. A novel verification algorithm is implemented based on analytical model cali...

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Bibliographic Details
Published in2020 42nd Annual EOS/ESD Symposium (EOS/ESD) pp. 1 - 6
Main Authors Marreiro, David, Malobabic, Slavica, Vashchenko, Vladislav
Format Conference Proceeding
LanguageEnglish
Published EOS/ESD Association 13.09.2020
Subjects
Analytical models
Current measurement
Design tools
Floors
Layout
Planning
Qualifications
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Summary:Unexpected latchup qualification test failures of HV analog integrated circuit were observed and explained by a new mechanism - injection current upset of internal HV blocks resulting in overload and burnout of LV circuits. A novel verification algorithm is implemented based on analytical model calibrated with latchup test structures data.