A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

• Published in: 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) pp. 66 - 67
• Main Authors: Zerbe, J.L., Chau, P.S., Werner, C.W., Stonecypher, W.F., Liaw, H.J., Gong Jong Yeh, Thrush, T.P., Best, S.C., Donnelly, K.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2001
• Subjects: Attenuation; Crosstalk; Eyes; Frequency; Intersymbol interference; Master-slave; MOS devices; Packaging; System testing; Transmitters

A 2 Gb/s/pin single-ended 4-PAM parallel bus interface uses transmit crosstalk cancellation and equalization techniques as well as integrating data receivers to improve system margin in low-cost packaging despite inherent coupling noise and data distortion.