A 7-nm 4-GHz Arm^1-Core-Based CoWoS^1 Chiplet Design for High-Performance Computing

• Published in: IEEE journal of solid-state circuits pp. 1 - 11
• Main Authors: Lin, Mu-Shan, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi
• Format: Journal Article
• Language: English
• Published: IEEE 26.02.2020
• Subjects: Chip-on-Wafer-on-Substrate (CoWoS); Clocks; Computer architecture; delay-locked loop (DLL); heterogeneous integration; Integrated circuit interconnections; interposer; low-swing IO; Metals; microbump; Microprocessors; phase-locked loop (PLL); system-in-package (SiP); Timing; Tuning
• DOI: 10.1109/JSSC.2019.2960207
• ISSN: 0018-9200

We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low-voltage-In-Package-INterCONnect (LIPINCON) clock-forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3-V transmitter swing without receiver termination to achieve 0.56-pJ/bit energy efficiency and 1.6-Tb/s/mm² bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on-die data bus, and inter-chiplet link. The built-in LIPINCON eye-scan feature validates inter-chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI.