Low-temperature off-state bipolar effect in floating-body PD/SOI MOSFETs - Pelella, M.M.; Fossum, J.G.; Chuang, C.T.; Torreiter, O.A.; Schettler, H.; Puri, R.; Ketchen, M.B.; Rosenfield, M.G. (2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125), 2000)
One option to counter the slowing CMOS scaling trend is to reduce the ambient temperature (T) of the semiconductor chip. At low operating T, increased carrier mobility, subthreshold slope, and threshold voltage (V/sub t/) have been demonstrated for bulk-Si MOSFETs (Sun et al., 1987), thus enhancing drive current, allowing lower-V/sub t/ design, and providing significant improvement in the speed-power performance of the technology, especially for the same-off-current T-scaling scenario (Taur and Nowak, 1997). In this paper, the behavior of floating-body (FB) partially depleted (PD) SOI CMOS is evaluated at low T down to -100/spl deg/C, which reflects a practical operating temperature range subject to the cost of the required cooling system. Results show that the negative T-coefficient of the FB voltage V/sub BS/(T) (Pelella et al, 1998) can lead to activation of the parasitic bipolar transistor (BJT), inducing an anomalous subthreshold current characteristic as T is reduced. They further reveal an increasing off-state current (I/sub off/), below a critical T, which implies a possible limit to the low-T operating range of FB PD/SOI CMOS. However, we show that device optimization can ameliorate this low-T bipolar effect, enabling a lower-T operating range and a significantly enhanced circuit performance.