Dual damascene architectures evaluation for the 0.18 /spl mu/m technology and below

• Published in: Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) pp. 267 - 269
• Main Authors: Verove, C., Descouts, B., Gayet, P., Guillermet, M., Sabouret, E., Spinelli, E., Van der Vegt, E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Copper; Costs; Etching; Lithography; Logic devices; Manufacturing; Robustness; Silicon compounds; Testing; Yield estimation

This paper compares three different schemes to pattern dual damascene (DD) structures. The Self Aligned (SA), Via First (VF), and Trench First (TF) architectures are compared in terms of complexity, process latitude, and sensitivity to lithography misalignment using 0.18-/spl mu/m copper/oxide two m...