Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee

• Published in: 2018 IEEE International Solid-State Circuits Conference - (ISSCC) pp. 100 - 101
• Main Authors: Meghelli, Mounir, Bae, Hyeon-Min, O'Mahony, Frank
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2018
• DOI: 10.1109/ISSCC.2018.8310203

High-speed serial I/Os continue to be pushed to higher bandwidth and density for every new generation of systems, which enable the scaling of data centers, fueled by a world that is becoming increasingly connected and digital. This session starts with the presentation of two low-power transmitters demonstrating a data rate of 112Gb/s using PAM-4 modulation, both implemented in advanced CMOS FinFet technologies. It continues with a presentation of a multi-standard 4-lane 1.25-to-28.05Gb/s transceiver designed in 14nm CMOS FinFET technology and supporting up to 40dB of channel loss at a power efficiency of 6pJ/b. Three papers describing PAM-4 transceivers are presented next, two implemented in 16nm CMOS FinFET technology targeting long reach links at 56Gb/s and 64Gb/s respectively, and one implemented in 28nm CMOS FDSOI targeting 64Gb/s short reach links. Finally, the session concludes with a paper describing a 4.16pJ/b 32Gb/s PAM-4 transceiver implemented in 65nm CMOS technology.