14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems

• Published in: 2017 IEEE International Solid-State Circuits Conference (ISSCC) pp. 238 - 239
• Main Authors: Desoli, Giuseppe, Chawla, Nitin, Boesch, Thomas, Singh, Surinder-pal, Guidetti, Elio, De Ambroggi, Fabio, Majo, Tommaso, Zambotti, Paolo, Ayodhyawasi, Manuj, Singh, Harvinder, Aggarwal, Nalin
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2017
• Subjects: Convolution; Digital signal processing; Kernel; Memory management; Neural networks; Power demand; Throughput
• DOI: 10.1109/ISSCC.2017.7870349

A booming number of computer vision, speech recognition, and signal processing applications, are increasingly benefiting from the use of deep convolutional neural networks (DCNN) stemming from the seminal work of Y. LeCun et al. [1] and others that led to winning the 2012 ImageNet Large Scale Visual Recognition Challenge with AlexNet [2], a DCNN significantly outperforming classical approaches for the first time. In order to deploy these technologies in mobile and wearable devices, hardware acceleration plays a critical role for real-time operation with very limited power consumption and with embedded memory overcoming the limitations of fully programmable solutions.