27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration

• Published in: 2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 468 - 469
• Main Authors: Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2016
• Subjects: Bandwidth; Calibration; Capacitors; Charge pumps; Hardware; Solid state circuits; Switches
• DOI: 10.1109/ISSCC.2016.7418110
• ISBN: 1467394661; 9781467394666

Recent radio architectures, such as WiGig and 5G, require ADCs with bandwidth beyond 1GHz and ENOB of 6-to-8b while retaining excellent power efficiency for long battery life. Therefore, many time-interleaved SAR ADCs are used in a distributed sampling scheme, leaving the timing-skew problem to be resolved by calibration. Only a few timing-skew calibration algorithms have been reported for interleaved ADCs to correct timing error in the analog domain [1,2] or in the digital domain [3]. The drawback of analog correction includes the feedback-induced stability hazard and jitter introduced by the controlled delay line. Digital-domain correction takes advantage of technology scaling but the complex slope-extraction filter limits signal bandwidth. The reported ADC demonstrates a digital timing-skew correction technique incorporated with a delta-sampling technique, and achieves a 2.6GHz sampling rate and a wide signal bandwidth.