2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS

• Published in: 2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 52 - 54
• Main Authors: Sievert, Sebastian, Degani, Ofir, Ben-Bassat, Assaf, Banin, Rotem, Ravi, Ashoke, Klepser, Bernd-Ulrich, Boos, Zdravko, Schmitt-Landsiedel, Doris
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2016
• Subjects: CMOS integrated circuits; Delays; Interpolation; Phase locked loops; Signal resolution; Solid state circuits; Tuning

Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2], in the feedback or reference path of a phase-locked loop (PLL) [3,4] or as direct phase modulators in outphasing trans...