2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS

Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2], in the feedback or reference path of a phase-locked loop (PLL) [3,4] or as direct phase modulators in outphasing trans...

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Bibliographic Details
Published in2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 52 - 54
Main Authors Sievert, Sebastian, Degani, Ofir, Ben-Bassat, Assaf, Banin, Rotem, Ravi, Ashoke, Klepser, Bernd-Ulrich, Boos, Zdravko, Schmitt-Landsiedel, Doris
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2016
Subjects
CMOS integrated circuits
Delays
Interpolation
Phase locked loops
Signal resolution
Solid state circuits
Tuning
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Summary:Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2], in the feedback or reference path of a phase-locked loop (PLL) [3,4] or as direct phase modulators in outphasing transmitters (OT) [5]. While DTCs in PLLs often operate close to the reference oscillator frequency, CDR and OT DTCs are required to operate at frequencies in the GHz range. DTCs are often built using a multistage segmented architecture, employing separate coarse and fine delay tuning.
ISBN:1467394661
9781467394666
ISSN:2376-8606
DOI:10.1109/ISSCC.2016.7417902