Rapid in-line characterization of plasma-induced damage on a 0.25 /spl mu/m CMOS ASIC technology

• Published in: 1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100) pp. 148 - 151
• Main Authors: Liang, V., Bothra, S., Sur, H., Sengupta, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1998
• Subjects: Application specific integrated circuits; CMOS process; CMOS technology; Metallization; Plasma density; Plasma materials processing; Plasma measurements; Plasma sources; Routing; Testing
• ISBN: 0965157725; 9780965157728
• DOI: 10.1109/PPID.1998.725596

An investigation into CMOS gate oxide failures during the process development of an advanced 0.25/spl mu/m CMOS ASIC process is presented. Using a SEM technique called passive voltage contrast (PVC), specific backend process steps contributing to the failures were rapidly identified as titanium deposition and SiN deposition. Both these processes are plasma based processes and the failures were addressed by applying a basic understanding of plasma charging induced damage mechanisms. This case study demonstrates the value of PVC in the rapid in-line characterization of gate oxide integrity, and in facilitating quick-turn isolation and elimination of the sources of damage.