Trends in High Density DRAMs

• Published in: ESSCIRC '84: Tenth European Solid-State Circuits Conference pp. 132 - 139
• Main Authors: Ishihara, Masamichi, Kawamoto, Hiroshi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.1984
• Subjects: Alpha particles; Capacitance; Capacitors; Circuits; Dielectrics; Extrapolation; Packaging; Production; Random access memory; Silicon compounds

This paper presents a technical perspective for a high density DRAM especially a IM DRAM. From extrapolation of past trends in memory capacity vs. size, chip size will be 50 to 60 mm 2 . This will be realized by improving the cell structure, the dieletric layer for a cell or both. The good candidates are the corrugated capacitor cell (CCC) and stacked capacitor cell (STC). In transistor technology, a lightly doped drain will be a standard device for maintaining stable threshold voltage in spite of short channel transistor such as 1.0 μm. Circuit innovations needed to improve bit line to cell capacitance ratio are a new column decoder circuit and a sense amplifier with short bit lines utilizing multilevel Al layers. Redundancy technique will become more popular than 256K DRAMs.