An MSB-first 1-of-N single-track asynchronous Add-Compare-Select unit for Viterbi decoders

In this paper, a new Add-Compare-Select unit for Viterbi decoder is presented. By implementing carry-save addition and most-significant-bit-first (MSB-First) comparison with 1-of-N asynchronous single track template, the computation speed can vary with different input data patterns, and thus perform...

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Bibliographic Details
Published in2009 International Conference on Communications, Circuits and Systems pp. 361 - 364
Main Authors Sheng-Yao Cheng, Chin-Khai Tang, Yi-Chang Lu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2009
Subjects
Asynchronous circuits
Decoding
Delay
Equations
Feedback loop
MOSFETs
Signal design
Timing
Viterbi algorithm
Wire
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Summary:In this paper, a new Add-Compare-Select unit for Viterbi decoder is presented. By implementing carry-save addition and most-significant-bit-first (MSB-First) comparison with 1-of-N asynchronous single track template, the computation speed can vary with different input data patterns, and thus performance improves considerably. A comparison between different circuit styles is also provided, which shows the performance of our design is potentially better than other designs.
ISBN:1424448867
9781424448869
DOI:10.1109/ICCCAS.2009.5250497