Design and manufacturing considerations of a 0.5 /spl mu/m CMOS technology on TFSOI

• Published in: Proceedings of 1993 IEEE International SOI Conference pp. 128 - 129
• Main Authors: Bor-Yuan Hwang, Jenn Tsao, Racanelli, M., Huang, M., Foerstner, J., Wetteroth, T., Ik-Sung Lim
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1993
• Subjects: CMOS technology; Costs; Geometry; Physics; Pulp manufacturing; Radiation hardening; Semiconductor device modeling; Silicon; Thick films; Transistors
• ISBN: 9780780313460; 0780313461
• DOI: 10.1109/SOI.1993.344565

While thin film SOI (TFSOI) advantages over bulk technology have been reported over the past many years, the TFSOI commodity products are yet to be introduced. Applications of SOI remain in the thick film rad-hard oriented niche market. Theoretical study and silicon implementation of SOI physics and a cost model have for the most part supported the advantages of TFSOI. This paper discusses considerations for the SOI manufacturing feasibility, and the implication to the TFSOI product introduction. The emphasis is placed on the 0.5 /spl mu/m level since this is the state-of-the-art geometry for production of bulk CMOS. Also the huge capital expense for a fabrication line at 0.5 /spl mu/m and beyond will inevitably prolong the technology lifetime and call for value added technology. TFSOI technology at 0.5 /spl mu/m fits into the above category.< >