Complexity/performance tradeoffs with non-blocking loads

• Published in: Proceedings of 21 International Symposium on Computer Architecture pp. 211 - 222
• Main Authors: Farkas, K.I., Jouppi, N.P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1994
• Subjects: Buffer storage; Costs; Delay; Educational institutions; Hardware; Instruments; Microprocessors; Processor scheduling; Registers
• DOI: 10.1109/ISCA.1994.288148
• ISBN: 9780818655104; 0818655100

Non-blocking loads are a very effective technique for tolerating the cache-miss latency on data cache references. The authors describe several methods for implementing non-blocking loads. A range of resulting hardware complexity/performance tradeoffs are investigated using an object-code translation and instrumentation system. The authors investigate the SPEC92 benchmarks and have found that for the integer benchmarks, a simple hit-under-miss implementation achieves almost all of the available performance improvement for relatively little cost. However, for most of the numeric benchmarks, more expensive implementations are worthwhile. The results also point out the importance of using a compiler capable of scheduling load instructions for cache misses rather than cache hits in non-blocking systems.< >