Optimization of 2.14 um/sup 2/ 6T-SRAM cell by using cell-like test structures

• Published in: Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516) pp. 211 - 215
• Main Authors: Hsieh, S., Tsui, R.F., Lin, W., Liaw, J.J., Doong, K.Y., Wu, C.-M.M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Circuits; Contacts; Costs; Dielectric measurements; Electric variables measurement; Kelvin; Logic testing; Random access memory; Routing; Variable structure systems
• DOI: 10.1109/ICMTS.2004.1309481
• ISBN: 9780780382626; 0780382625

This work is aimed at describing the optimization of a shrunk version of an embedded 6T-SRAM-cell process and the evaluation of yield impact by using cell-like test structures. The various test structures are designed to narrow down the cell characteristics and the electrical performance. These test structures are also used for evaluating the integration process as well. This article also reveals the concerns and trade-offs of SRAM cell-like test-structures design and their electrical measurements. The means to evaluate the design-rule and optimize the process-windows by using the electrical measurements as screening criteria, that of the complete set of SRAM cell-like test structures, are proposed in this work.