Energy-Efficient MAC Operation Using Double Data Rate SOT-Based Magnetic RAM - Sehgal, Anubha; Soni, Sandeep; Shukla, Alok Kumar; Roy, Sourajeet (Proceedings of the ... IEEE Conference on Nanotechnology, 2025)
In a von Neumann architecture, the processor and memory share the same bus for data transfer, which causes a significant performance bottleneck when accessing memory. In-memory computing overcomes this limitation but still faces challenges, particularly the large latency in performing computations within memory. To address this issue, a double data rate (DDR) architecture that leverages spin-orbit torque technology (SOT) has been integrated into the memory design, enabling simultaneous write and read operations at both clock levels. SOT-magnetic random-access memory (MRAM) based DDR technology presents a promising approach for developing high-density and low power consumption in non-volatile memory, making it a more efficient memory solution. Furthermore, the presented DDR-SOT-based MRAM has been used to design the multiply and accumulate computation (MAC). The performance metrics in terms of latency and power dissipation are also calculated. The proposed circuit consumes 7.9 μ W of power with a latency of 90 ps, making it a suitable candidate for enhancing the performance of neural network applications.