Two-Stage Transconductance Operational Amplifier designed with VFET experimental data

• Published in: 2024 38th Symposium on Microelectronics Technology and Devices (SBMicro) pp. 1 - 4
• Main Authors: Ribeiro, Arllen D. R., Silva, Vanessa C.P., Martino, Joao A., Veloso, Anabela, Horiguchi, Naoto, Agopian, Paula G. D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 02.09.2024
• Subjects: Circuit optimization; Logic gates; Microelectronics; Nanoscale devices; Operational amplifiers; Power dissipation; Threshold voltage; transconductance operational circuit; transistors with gate-all-around; vertical nanowires
• ISSN: 2832-4218
• DOI: 10.1109/SBMicro64348.2024.10673846

In this paper, the design of a Two-Stage Transconductance Operational Amplifier (OTA) was studied, using vertical nanowire experimental data. The vertical nanowire device was investigated in both its forward and reverse mode. After analyzing the main electrical parameters of the devices such as Threshold Voltage (V TH ), Drain Current (I DS ), Transconductance (gm), Output Conductance (gd), Early Voltage (V EA ), and Intrinsic Voltage Gain (Av) of the device, it was concluded that, that, for analog integrated circuit applications, the best configuration is in the forward mode thanks to presenting a higher intrinsic voltage gain. Once the best mode for the vertical nanowire was chosen, three OTA circuits were designed, varying the quantity of vertical nanowires among them, to observe how the area affects circuit performance by analyzing its key operating parameters such as voltage gain (Av), gain-bandwidth product (GBW), phase margin (PM), and power dissipation (PD). As a result, it was observed that for a larger area, there is a higher GBW reaching 2GHz; however, the integrated circuit has a higher power dissipation, reaching 4000μW due to the increase in current caused by the number of added parallel devices.