A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

• Published in: 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
• Main Authors: Lin, Mu-Shan, Tsai, Chien-Chun, Li, Shenggao, Huang, Tze-Chiang, Huang, Wen-Hung, Huang, Kate, Chen, Yu-Chi, Liu, Alex, Huang, Yu-Jie, Wang, Jimmy, Yang, Shu-Chun, Cheng, Nai-Chen, Li, Chao-Chieh, Kuo, Hsin-Hung, Chen, Wei-Chih, Wen, C.H., Lin, Kevin, Huang, Po-Yi, Hsieh, Kenny Cheng-Hsiang, Lee, Frank
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16.06.2024
• Subjects: Aggregates; Bandwidth; Random access memory; Scalability; Stacking; Three-dimensional displays; Very large scale integration
• DOI: 10.1109/VLSITechnologyandCir46783.2024.10631440

This paper presents a die-to-die link with a compute die in 5nm FinFET and a SRAM die in 6nm FinFET, with a face-to-back 3D stacking at a 9μm bond pitch. Modular design that supports full scalability is demonstrated, achieving a 10.24Tb/s aggregate bandwidth for 320 Tx lanes and 320 Rx lanes, at a PAM-4 16Gb/s per lane data rate. Each data cluster is designed with 80 Tx/Rx lanes in a 378μm*378μm footprint, achieving a bandwidth density of 17.9Tb/s/mm2 and an energy efficiency of 0.296pJ/bit per link.