IMAGE FORMING APPARATUS

Data from a drawing engine main part (101) is sent to a FIFO (First In First Out) memory (102), temporarily stored there and sent to a high speed cache memory (104) through an arithmetic unit (103). Data are transmitted between this cache memory (104) and a frame buffer (105). A cache controller (10...

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Main Authors HIROI, TOSHIYUKI, OKA, MASAAKI
Format Patent
LanguageEnglish
French
Japanese
Published 14.08.1997
Edition6
Subjects
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Abstract Data from a drawing engine main part (101) is sent to a FIFO (First In First Out) memory (102), temporarily stored there and sent to a high speed cache memory (104) through an arithmetic unit (103). Data are transmitted between this cache memory (104) and a frame buffer (105). A cache controller (106) prefetches the contents of the FIFO memory (102) and controls the cache memory (104) so that all the data of the same page which is stored inside the frame buffer (105) and to which high speed access can be made can be read and written. In this way, high speed access can be made and the drawing speed can be improved though an economical frame buffer is used. La présente invention consiste à envoyer à une mémoire à pile en liste directe ou "FIFO" (102), des données issues du module principal (101) d'un moteur de dessin, à les y stocker temporairement et à les envoyer à une antémémoire haute vitesse (104) via une unité arithmétique (103). Les données sont transmises entre cette antémémoire (104) et un tampon de trame (105). Un contrôleur d'antémémoire (106), qui assure la prélecture du contenu de la mémoire FIFO (102), gère l'antémémoire (104) de façon que toutes les données d'une même page soient stockées dans le même tampon de trame (105), ce qui autorise des accès, des lectures et des écritures à grande vitesse. Grâce à son tampon de trame économique, cette architecture permet des accès à grande vitesse et améliore la vitesse de dessin.
AbstractList Data from a drawing engine main part (101) is sent to a FIFO (First In First Out) memory (102), temporarily stored there and sent to a high speed cache memory (104) through an arithmetic unit (103). Data are transmitted between this cache memory (104) and a frame buffer (105). A cache controller (106) prefetches the contents of the FIFO memory (102) and controls the cache memory (104) so that all the data of the same page which is stored inside the frame buffer (105) and to which high speed access can be made can be read and written. In this way, high speed access can be made and the drawing speed can be improved though an economical frame buffer is used. La présente invention consiste à envoyer à une mémoire à pile en liste directe ou "FIFO" (102), des données issues du module principal (101) d'un moteur de dessin, à les y stocker temporairement et à les envoyer à une antémémoire haute vitesse (104) via une unité arithmétique (103). Les données sont transmises entre cette antémémoire (104) et un tampon de trame (105). Un contrôleur d'antémémoire (106), qui assure la prélecture du contenu de la mémoire FIFO (102), gère l'antémémoire (104) de façon que toutes les données d'une même page soient stockées dans le même tampon de trame (105), ce qui autorise des accès, des lectures et des écritures à grande vitesse. Grâce à son tampon de trame économique, cette architecture permet des accès à grande vitesse et améliore la vitesse de dessin.
Author HIROI, TOSHIYUKI
OKA, MASAAKI
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RelatedCompanies SONY COMPUTER ENTERTAINMENT INC
HIROI, TOSHIYUKI
OKA, MASAAKI
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Snippet Data from a drawing engine main part (101) is sent to a FIFO (First In First Out) memory (102), temporarily stored there and sent to a high speed cache memory...
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SubjectTerms ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CALCULATING
COMPUTING
COUNTING
CRYPTOGRAPHY
DISPLAY
EDUCATION
ELECTRIC DIGITAL DATA PROCESSING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
SEALS
Title IMAGE FORMING APPARATUS
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