TECHNOLOGIES FOR NIC PORT REDUCTION WITH ACCELERATED SWITCHING

• Main Authors: GADIYAR, Rajesh, CHIEN, Shih-Wei, PALERMO, Stephen T, MEHTA, Deepal, LIEW, Irene, ROGERS, Gerald, VENKATESAN, Namakkal N
• Format: Patent
• Language: English; French
• Published: 29.08.2019
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

Technologies for accelerated network processing include a computing device having a processor and an accelerator. The accelerator may be a field-programmable gate array (FPGA). The accelerator includes a virtual switch and a network port, such as an Ethernet physical interface. The network port of t...