PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Provided is an SGT circuit having: first conductor layers (15a, 21) which include semiconductor atoms of Si and are in contact with an N+ region (2a), a P+ region (3a) or a TiN layer (10d) of a Si pillar 6, and outer circumferences of which are further outward than the outer circumference of a SiO2...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English French Japanese |
Published |
04.10.2018
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | Provided is an SGT circuit having: first conductor layers (15a, 21) which include semiconductor atoms of Si and are in contact with an N+ region (2a), a P+ region (3a) or a TiN layer (10d) of a Si pillar 6, and outer circumferences of which are further outward than the outer circumference of a SiO2 layer (11d), in a plan view; and a second conductor layer (22) which includes metal atoms of Ni is connected to outer circumferential sections of the first conductor layers (15a, 21), and extends in the horizontal direction.
L'invention concerne un circuit SGT comportant : des premières couches conductrices (15a, 21) qui comprennent des atomes semi-conducteurs de Si et sont en contact avec une région N+ (2a), une région P+ (3a) ou une couche de TiN (10d) d'un pilier en Si (6), dont les circonférences extérieures sont davantage vers l'extérieur que la circonférence extérieure d'une couche de SiO2 (11d), dans une vue en plan ; et une deuxième couche conductrice (22), qui comprend des atomes métalliques de Ni, est reliée à des sections circonférentielles extérieures des premières couches conductrices (15a, 21), et se prolonge dans la direction horizontale.
Si柱6のN+領域(2a)、P+領域(3a)、またはTiN層(10d)に接し、且つ、平面視において、その外周がSiO2層(11d)の外周より外側にある半導体原子Siを含む第1の導体層(15a、21)と、第1の導体層(15a、21)の外周部に繋がり、水平方向に伸延する金属原子Niを含む第2の導体層(22)を有したSGT回路。 |
---|---|
AbstractList | Provided is an SGT circuit having: first conductor layers (15a, 21) which include semiconductor atoms of Si and are in contact with an N+ region (2a), a P+ region (3a) or a TiN layer (10d) of a Si pillar 6, and outer circumferences of which are further outward than the outer circumference of a SiO2 layer (11d), in a plan view; and a second conductor layer (22) which includes metal atoms of Ni is connected to outer circumferential sections of the first conductor layers (15a, 21), and extends in the horizontal direction.
L'invention concerne un circuit SGT comportant : des premières couches conductrices (15a, 21) qui comprennent des atomes semi-conducteurs de Si et sont en contact avec une région N+ (2a), une région P+ (3a) ou une couche de TiN (10d) d'un pilier en Si (6), dont les circonférences extérieures sont davantage vers l'extérieur que la circonférence extérieure d'une couche de SiO2 (11d), dans une vue en plan ; et une deuxième couche conductrice (22), qui comprend des atomes métalliques de Ni, est reliée à des sections circonférentielles extérieures des premières couches conductrices (15a, 21), et se prolonge dans la direction horizontale.
Si柱6のN+領域(2a)、P+領域(3a)、またはTiN層(10d)に接し、且つ、平面視において、その外周がSiO2層(11d)の外周より外側にある半導体原子Siを含む第1の導体層(15a、21)と、第1の導体層(15a、21)の外周部に繋がり、水平方向に伸延する金属原子Niを含む第2の導体層(22)を有したSGT回路。 |
Author | MASUOKA Fujio HARADA Nozomu |
Author_xml | – fullname: MASUOKA Fujio – fullname: HARADA Nozomu |
BookMark | eNrjYmDJy89L5WRwCfD08XEM0g32cAxwdVEIdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UXADivo6-oW6OTqHhAZ5-rkrBDv6uvIwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvhwfyMDQwtDc0sDIzNHQ2PiVAEAJg0uaw |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
DocumentTitleAlternate | DISPOSITIF À SEMI-CONDUCTEUR EN FORME DE PILIER ET SON PROCÉDÉ DE FABRICATION 柱状半導体装置と、その製造方法 |
ExternalDocumentID | WO2018179026A1 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_WO2018179026A13 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 12:47:41 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English French Japanese |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_WO2018179026A13 |
Notes | Application Number: WO2017JP12244 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181004&DB=EPODOC&CC=WO&NR=2018179026A1 |
ParticipantIDs | epo_espacenet_WO2018179026A1 |
PublicationCentury | 2000 |
PublicationDate | 20181004 |
PublicationDateYYYYMMDD | 2018-10-04 |
PublicationDate_xml | – month: 10 year: 2018 text: 20181004 day: 04 |
PublicationDecade | 2010 |
PublicationYear | 2018 |
RelatedCompanies | UNISANTIS ELECTRONICS SINGAPORE PTE. LTD MASUOKA Fujio HARADA Nozomu |
RelatedCompanies_xml | – name: HARADA Nozomu – name: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD – name: MASUOKA Fujio |
Score | 3.2887218 |
Snippet | Provided is an SGT circuit having: first conductor layers (15a, 21) which include semiconductor atoms of Si and are in contact with an N+ region (2a), a P+... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181004&DB=EPODOC&locale=&CC=WO&NR=2018179026A1 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwEA9jivqmU_FjSkDZW7Fb22U-DMmSlCr0g62dexvNmoEi23AV_30vsdM97S3JwZFcuNz9kl8ShO69Qh9GdXJr3la55TrEs6SyC6voKUUI5M9KGpZv1A0y92XiTWroY3MXxrwT-m0eRwSPmoG_l2a9Xv1vYnHDrVw_yDdoWj75aZ-3KnQM4UpPOh_0RRLzmLUYA9zWioa_MvIIiIMCVtqDRJoY2DYe6Hspq-2g4h-j_QT0LcoTVHvPG-iQbf5ea6CDsDryhmLlfetTxBOA3nRojQKaCI5H2oRxxDOWxkPMxfiZCUwjjkORBjHHgO9wSKPMpyzNNOkBj2goztCdL1IWWNCd6d_op6_xdt-dc1RfLBfqAuH23GtLR3ZI7hSuXRS57c0caffI3O7qj_ouUXOXpqvd4mt0pKuGt-Y2Ub38_FI3EH9LeWvM9gPcu4JG |
link.rule.ids | 230,309,783,888,25577,76883 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dT8IwEL8QNOKbosYP1CYa3hYH2xg-EDPaLkPZR2BD3sjKSqIxQGTGf99bBeWJt6aXXNprrtdf79cewL2VFcmoZqrNGjLVTMO2NCH1TMvaUto2np-lUCzfoOUl5vPYGpfgY_MWRv0T-q0-R0SPmqK_52q_Xv5fYjHFrVw9iDfsWjy5cYfV1-gYw1Wx6Kzb4VHIQlqnFHFbPRj8yuxHRBwOYqU9PGS3FVgadYt3KcvtoOIewX6E-ub5MZTe0ypU6Kb2WhUO_HXKG5tr71udAIsQejsDbeg5EWdkWJgwDFhC43BAGB_1KCdOwIjPYy9kBPEd8Z0gcR0aJwXpgQwdn5_Cnctj6mk4nMnf7Cev4fbYjTMozxdzeQ6kMbMawhBNOzUyU8-yVLemhtDb9kxvFYX6LqC2S9PlbvEtVLzY70_6veDlCg4LkeKwmTUo559f8hpjcS5ulAl_ACEMhTY |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=PILLAR-SHAPED+SEMICONDUCTOR+DEVICE+AND+METHOD+FOR+MANUFACTURING+SAME&rft.inventor=MASUOKA+Fujio&rft.inventor=HARADA+Nozomu&rft.date=2018-10-04&rft.externalDBID=A1&rft.externalDocID=WO2018179026A1 |