HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGEMENT UNITS AND DISTRIBUTED VIRTUAL MEMORY NETWORKS

• Main Authors: SOMASUNDARAM, Manokanthan, PODAIMA, Jason Edward, RAMKUMAR, Myil, HALTER, Steven John, SUBRAMANIAM GANASAN, Jaya Prakash, WIERCIENSKI, Paul Christopher John, AVOINNE, Christophe Denis Bernard, PAL, Dipti Ranjan, RYCHLIK, Bohuslav, DENA, Sina
• Format: Patent
• Language: English; French
• Published: 05.10.2017
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, th...