THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES
In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistiv...
Saved in:
Main Authors | , , , , , , , |
---|---|
Format | Patent |
Language | English French |
Published |
07.05.2015
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile, The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.
Selon un exemple, l'invention concerne une architecture de mémoire résistive tridimensionnelle qui inclut des tuiles de mémoire adjacentes incluant chacune une barrette transversale multiniveau résistive et au moins un décodeur. La barrette transversale multiniveau inclut des couches transversales de ligne, des couches transversales de colonne, et des couches d'éléments de mémoire résistifs intercalés entre les points d'intersection des éléments transversaux de ligne et des éléments transversaux de colonne, de sorte qu'au moins une couche transversale s'étend depuis une première tuile à travers une tuile adjacente et est utilisée pour adresser des éléments de mémoire résistifs dans la tuile adjacente. Le(s) décodeur(s) est (sont) sous-jacent(s) à la barrette transversale multiniveau résistive et inclu(en)t une matrice d'adresse comprenant des lignes numériques et des lignes analogiques, de sorte que les lignes numériques sélectionnent quels éléments transversaux sont connectés aux lignes analogiques. |
---|---|
AbstractList | In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile, The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.
Selon un exemple, l'invention concerne une architecture de mémoire résistive tridimensionnelle qui inclut des tuiles de mémoire adjacentes incluant chacune une barrette transversale multiniveau résistive et au moins un décodeur. La barrette transversale multiniveau inclut des couches transversales de ligne, des couches transversales de colonne, et des couches d'éléments de mémoire résistifs intercalés entre les points d'intersection des éléments transversaux de ligne et des éléments transversaux de colonne, de sorte qu'au moins une couche transversale s'étend depuis une première tuile à travers une tuile adjacente et est utilisée pour adresser des éléments de mémoire résistifs dans la tuile adjacente. Le(s) décodeur(s) est (sont) sous-jacent(s) à la barrette transversale multiniveau résistive et inclu(en)t une matrice d'adresse comprenant des lignes numériques et des lignes analogiques, de sorte que les lignes numériques sélectionnent quels éléments transversaux sont connectés aux lignes analogiques. |
Author | PERNER, FREDERICK CHUNG, SUNG WON LEE, JAE YEON PARK, JINWON KIM, JEONG HWAN HWANG, SANGMIN RHO, KWANGMYOUNG YI, JAE YUN |
Author_xml | – fullname: YI, JAE YUN – fullname: CHUNG, SUNG WON – fullname: KIM, JEONG HWAN – fullname: PARK, JINWON – fullname: RHO, KWANGMYOUNG – fullname: PERNER, FREDERICK – fullname: HWANG, SANGMIN – fullname: LEE, JAE YEON |
BookMark | eNrjYmDJy89L5WQwCPEIcnVVcPH0dfUL9vT3c_RRCHIN9gwO8QxzVfB19fUPilRwDHL28AxxdQ4JBUrxMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JL4cH8jA0NTAzNTExNjR0Nj4lQBAPEyKVk |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
DocumentTitleAlternate | ARCHITECTURES DE MÉMOIRE RÉSISTIVE TRIDIMENSIONNELLES |
ExternalDocumentID | WO2015065443A1 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_WO2015065443A13 |
IEDL.DBID | EVB |
IngestDate | Fri Aug 23 06:56:39 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English French |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_WO2015065443A13 |
Notes | Application Number: WO2013US67823 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150507&DB=EPODOC&CC=WO&NR=2015065443A1 |
ParticipantIDs | epo_espacenet_WO2015065443A1 |
PublicationCentury | 2000 |
PublicationDate | 20150507 |
PublicationDateYYYYMMDD | 2015-05-07 |
PublicationDate_xml | – month: 05 year: 2015 text: 20150507 day: 07 |
PublicationDecade | 2010 |
PublicationYear | 2015 |
RelatedCompanies | HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P |
RelatedCompanies_xml | – name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P |
Score | 2.9813714 |
Snippet | In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150507&DB=EPODOC&locale=&CC=WO&NR=2015065443A1 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFD6MKeqbTsXLlILSt-LC2mV9GOLSlFZoO9o659PIugwE6Yar-Pc9iZ3uaW-5QC4HvnPJuQTgnrhUUErmllLGLRslpNUXxLaEg6OuTUSHquTkKO4FL_bzxJk04GOTC6PrhH7r4oiIqALxXml-vfp_xPJ0bOX6YfaOQ8tHPx94Zm0do3aD-o3pDQd8lHgJMxlDu82M09-5nir29oS20h4q0lThgY-HKi9ltS1U_GPYH-F6ZXUCDVm24JBt_l5rwUFUu7yxWaNvfQqdPEg5N7ww4nGma9gaSL8wy8MxNyIeJemboZw_yI2YimbIzuDO5zkLLNx6-nfT6Wuyfc7uOTTLZSkvwCDFXDiFnCFPIEhAKRYFYlM4fYkWT9cVl9DetdLV7ulrOFJdHcdH29CsPr_kDcraanarSfQDD3x8iQ |
link.rule.ids | 230,309,783,888,25576,76876 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFOebTsWPqQWlb8WFtev6MMSlKa2u7WjrnE8l7SoI0g1X8d_3Ejvd095CDi7Jwe8-krsLwC2xTG6aZK4JZ1zT0UJqA050jRs4a-mEd01RnOwHffdZf5wZswZ8rGthZJ_Qb9kcERGVI94rqa-X_5dYtsytXN1l7zi1uHeSoa3W0TF6N-jfqPZoyCahHVKVUozb1CD6pfVFs7cHjJV20Mk2BR7YdCTqUpabRsU5gN0J8iurQ2gUZRtadP33Whv2_PrJG4c1-lZH0E3ciDHF9nwWxLKHrYLy8-LEmzLFZ34YvSri8Qe1ERXZDPEx3Dgsoa6GS6d_J01fws199k6gWS7K4hQUks-5kRcZ6gSCAiz4W47Y5MagwIinZ_Ez6GzjdL6dfA0tN_HH6dgLni5gX5BkTp_ZgWb1-VVcot2tsisprh8R2398 |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=THREE+DIMENSIONAL+RESISTIVE+MEMORY+ARCHITECTURES&rft.inventor=YI%2C+JAE+YUN&rft.inventor=CHUNG%2C+SUNG+WON&rft.inventor=KIM%2C+JEONG+HWAN&rft.inventor=PARK%2C+JINWON&rft.inventor=RHO%2C+KWANGMYOUNG&rft.inventor=PERNER%2C+FREDERICK&rft.inventor=HWANG%2C+SANGMIN&rft.inventor=LEE%2C+JAE+YEON&rft.date=2015-05-07&rft.externalDBID=A1&rft.externalDocID=WO2015065443A1 |