THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES

In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistiv...

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Main Authors YI, JAE YUN, CHUNG, SUNG WON, KIM, JEONG HWAN, PARK, JINWON, RHO, KWANGMYOUNG, PERNER, FREDERICK, HWANG, SANGMIN, LEE, JAE YEON
Format Patent
LanguageEnglish
French
Published 07.05.2015
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Abstract In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile, The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines. Selon un exemple, l'invention concerne une architecture de mémoire résistive tridimensionnelle qui inclut des tuiles de mémoire adjacentes incluant chacune une barrette transversale multiniveau résistive et au moins un décodeur. La barrette transversale multiniveau inclut des couches transversales de ligne, des couches transversales de colonne, et des couches d'éléments de mémoire résistifs intercalés entre les points d'intersection des éléments transversaux de ligne et des éléments transversaux de colonne, de sorte qu'au moins une couche transversale s'étend depuis une première tuile à travers une tuile adjacente et est utilisée pour adresser des éléments de mémoire résistifs dans la tuile adjacente. Le(s) décodeur(s) est (sont) sous-jacent(s) à la barrette transversale multiniveau résistive et inclu(en)t une matrice d'adresse comprenant des lignes numériques et des lignes analogiques, de sorte que les lignes numériques sélectionnent quels éléments transversaux sont connectés aux lignes analogiques.
AbstractList In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile, The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines. Selon un exemple, l'invention concerne une architecture de mémoire résistive tridimensionnelle qui inclut des tuiles de mémoire adjacentes incluant chacune une barrette transversale multiniveau résistive et au moins un décodeur. La barrette transversale multiniveau inclut des couches transversales de ligne, des couches transversales de colonne, et des couches d'éléments de mémoire résistifs intercalés entre les points d'intersection des éléments transversaux de ligne et des éléments transversaux de colonne, de sorte qu'au moins une couche transversale s'étend depuis une première tuile à travers une tuile adjacente et est utilisée pour adresser des éléments de mémoire résistifs dans la tuile adjacente. Le(s) décodeur(s) est (sont) sous-jacent(s) à la barrette transversale multiniveau résistive et inclu(en)t une matrice d'adresse comprenant des lignes numériques et des lignes analogiques, de sorte que les lignes numériques sélectionnent quels éléments transversaux sont connectés aux lignes analogiques.
Author PERNER, FREDERICK
CHUNG, SUNG WON
LEE, JAE YEON
PARK, JINWON
KIM, JEONG HWAN
HWANG, SANGMIN
RHO, KWANGMYOUNG
YI, JAE YUN
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– fullname: RHO, KWANGMYOUNG
– fullname: PERNER, FREDERICK
– fullname: HWANG, SANGMIN
– fullname: LEE, JAE YEON
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DocumentTitleAlternate ARCHITECTURES DE MÉMOIRE RÉSISTIVE TRIDIMENSIONNELLES
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Snippet In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array...
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SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES
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