SEMICONDUCTOR STORAGE DEVICE
The present invention provides a loadless 4T-SRAM configured from a vertical transistor SGT, the loadless 4T-SRAM having a small SRAM cell area. A stick-type memory cell configured by using four MOS transistors, wherein: the MOS transistors are SGTs which are formed on a bulk substrate and of which...
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| Main Authors | , |
|---|---|
| Format | Patent |
| Language | English French Japanese |
| Published |
22.08.2013
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| Subjects | |
| Online Access | Get full text |
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