Semiconductor device isolation via depleted coupling layer

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate within the doped isolation barrier, having the first conductivity type, and in which a channel is...

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Main Authors Zhu Ronghua, Zuo Jiang-Kai, Yang Hongning, Lin Xin
Format Patent
LanguageEnglish
Published 10.04.2018
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Abstract A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate within the doped isolation barrier, having the first conductivity type, and in which a channel is formed during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate. The plurality of RESURF layers are arranged in a stack between the body region and the doped isolation barrier. The plurality of RESURF layers include an upper layer having a second conductivity type, a lower layer having the second conductivity type, and an isolation coupling layer disposed between the upper and lower layers, in contact with the doped isolation barrier, and having the first conductivity type.
AbstractList A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate within the doped isolation barrier, having the first conductivity type, and in which a channel is formed during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate. The plurality of RESURF layers are arranged in a stack between the body region and the doped isolation barrier. The plurality of RESURF layers include an upper layer having a second conductivity type, a lower layer having the second conductivity type, and an isolation coupling layer disposed between the upper and lower layers, in contact with the doped isolation barrier, and having the first conductivity type.
Author Zhu Ronghua
Lin Xin
Yang Hongning
Zuo Jiang-Kai
Author_xml – fullname: Zhu Ronghua
– fullname: Zuo Jiang-Kai
– fullname: Yang Hongning
– fullname: Lin Xin
BookMark eNrjYmDJy89L5WSwCk7NzUzOz0spTS7JL1JISS3LTE5VyCzOz0ksyczPUyjLTAQKFuSklqSmKCTnlxbkZOalK-QkVqYW8TCwpiXmFKfyQmluBgU31xBnD93Ugvz41OKCxOTUvNSS-NBgS0sTQ2NTAydDYyKUAABkijET
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US9941350B1
GroupedDBID EVB
ID FETCH-epo_espacenet_US9941350B13
IEDL.DBID EVB
IngestDate Fri Jul 19 16:50:45 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US9941350B13
Notes Application Number: US201715456168
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180410&DB=EPODOC&CC=US&NR=9941350B1
ParticipantIDs epo_espacenet_US9941350B1
PublicationCentury 2000
PublicationDate 20180410
PublicationDateYYYYMMDD 2018-04-10
PublicationDate_xml – month: 04
  year: 2018
  text: 20180410
  day: 10
PublicationDecade 2010
PublicationYear 2018
RelatedCompanies NXP USA, Inc
RelatedCompanies_xml – name: NXP USA, Inc
Score 3.1451042
Snippet A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and having a first conductivity type, a body...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Semiconductor device isolation via depleted coupling layer
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180410&DB=EPODOC&locale=&CC=US&NR=9941350B1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KFfWmVbG-2IPkFsw7qRCEvChCH5hGeivZZCMBSUKb6t93dkmrF70tszDMPmZnZmfnW4CHQjcVRg1LztG-ywazqJxq1JaLAu0N04o0o_y-YzK1xonxsjSXPSh3tTACJ_RLgCOiRmWo7604r5ufS6xAvK3cPNISSfVztHADqYuOVY6mo0iB54bzWTDzJd93k1iavrqjEZ7WpuJhoHTAvWgOsx--ebwopfltUaJTOJwjs6o9gx6rBnDs7z5eG8DRpMt3Y7NTvc05PMX8GXtdcXzWek1yxlWclLh1hLjks0yR2OAysJxk9ZZX2r6TjxRd6gsgUbjwxzIKsdoPeJXEe3H1S-hXdcWugNgWzTO9UFL-a62ToWvsOGam2swyNYp-2BCGf7K5_qfvBk74zPEUiarcQr9db9kdWtqW3os5-gamm4Pl
link.rule.ids 230,309,786,891,25594,76903
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFOebTsX5mQfpW7Hd-rEJRWi7MXXrhutkb6NJUylIW7ZO_30voZu-6Fu4wHH5uNxdkvsdwF3SMTVODUuN0b6rBreoGrWprSYJ2hveTiJGxX3HOLCGc-N5YS5qkG5zYSRO6JcER0SNYqjvpTyvi59LLF_-rVzf0xRJ-eMgdHylio51gaajKb7r9KcTf-IpnufMZ0rw6vR6eFqbmouB0p6NEaGMlN5ckZRS_LYogyPYnyKzrDyGGs-a0PC2hdeacDCu3ruxWane-gQeZuIbe54JfNZ8RWIuVJykuHWkuOQzjZBY4DLwmLB8IzJt38lHhC71KZBBP_SGKgqx3A14OZ_txO2cQT3LM34OxLZozDqJFomqtV2GrnG3azLd5pbZpuiHtaD1J5uLf_puoTEMx6Pl6Cl4uYRDMYviuUTXrqBerjb8Gq1uSW_kfH0D9o2Gzw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Semiconductor+device+isolation+via+depleted+coupling+layer&rft.inventor=Zhu+Ronghua&rft.inventor=Zuo+Jiang-Kai&rft.inventor=Yang+Hongning&rft.inventor=Lin+Xin&rft.date=2018-04-10&rft.externalDBID=B1&rft.externalDocID=US9941350B1