Field-effect transistor with aggressively strained fins

In a method for fabricating a field-effect transistor (FET) structure, forming a shallow trench isolation (STI) structure on a semiconductor substrate, wherein the STI structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (ART) trenches. The method fu...

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Bibliographic Details
Main Authors Reznicek Alexander, Hashemi Pouya, Khakifirooz Ali
Format Patent
LanguageEnglish
Published 02.01.2018
Subjects
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