Field-effect transistor with aggressively strained fins
In a method for fabricating a field-effect transistor (FET) structure, forming a shallow trench isolation (STI) structure on a semiconductor substrate, wherein the STI structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (ART) trenches. The method fu...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
02.01.2018
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Subjects | |
Online Access | Get full text |
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