Chip scale package and related methods

Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall;...

Full description

Saved in:
Bibliographic Details
Main Authors Su Bingzhi, Gochnour Derek, Kinsman Larry
Format Patent
LanguageEnglish
Published 05.09.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

Abstract Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.
AbstractList Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.
Author Gochnour Derek
Kinsman Larry
Su Bingzhi
Author_xml – fullname: Su Bingzhi
– fullname: Gochnour Derek
– fullname: Kinsman Larry
BookMark eNrjYmDJy89L5WRQc87ILFAoTk7MSVUoSEzOTkxPVUjMS1EoSs1JLElNUchNLcnITynmYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxUCdqXmpJfGhwZbmpiaWFsZOhsZEKAEA1eQotQ
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US9754983B1
GroupedDBID EVB
ID FETCH-epo_espacenet_US9754983B13
IEDL.DBID EVB
IngestDate Fri Jul 19 14:28:28 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US9754983B13
Notes Application Number: US201615210716
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170905&DB=EPODOC&CC=US&NR=9754983B1
ParticipantIDs epo_espacenet_US9754983B1
PublicationCentury 2000
PublicationDate 20170905
PublicationDateYYYYMMDD 2017-09-05
PublicationDate_xml – month: 09
  year: 2017
  text: 20170905
  day: 05
PublicationDecade 2010
PublicationYear 2017
RelatedCompanies SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
RelatedCompanies_xml – name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Score 3.103941
Snippet Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Chip scale package and related methods
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170905&DB=EPODOC&locale=&CC=US&NR=9754983B1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFPVNp-L8Ig_St2LbNFv7UISmLUPYB26VvY2mDViEWmzFf99L7KYv-hYSuFwO7uOX3OUA7phfeAV6NpPZGTVdydAO2hRRq0tzxx1JyxYKKE5no0nqPq7ZugflthZG_xP6qT9HRI3KUd9bba_rn0usSOdWNveixKm3h2QVREaHju2x5VvMiMIgXsyjOTc4D9KlMXtCsIRAyKMhAqU9jKLHShni51AVpdS_PUpyDPsLJFa1J9CT1QAO-bbx2gAOpt17Nw471WtOweAvZU0aFKkkyPIr2gGSVQXRxSiyIN-toJszIEm84hMTN9zsDrdJlzvW6Dn0EfPLCyCFkzk-83Kh6tAoFSKXwrWlkxUOUyHNEIZ_krn8Z-0KjpSUdJIUu4Z--_4hb9CrtuJWy-MLW_h6pw
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFOebTsX5mQfpW7Ftmq19KEI_RtW1G66TvY2mDViEOmzFf99r7KYv-hYSuFwO7uOX3OUAbpidWzl6NpXpKVVNwdAO6hRRq0kzwxwKTecNUIziYbgwH5Zs2YFiUwsj_wn9lJ8jokZlqO-1tNfrn0ssX-ZWVre8wKm3u3Hi-EqLjvWRZmtM8V0nmE39qad4nrOYK_ETgiUEQhZ1ESjtYIQ9apQheHabopT1b48yPoDdGRIr60PoiLIPPW_TeK0Pe1H73o3DVvWqI1C8l2JNKhSpIMjyK9oBkpY5kcUoIiffraCrYyDjIPFCFTdcbQ-3Wsy3rNET6CLmF6dAciM1bGZlvKlDo5TzTHBTF0aaG6wJaQYw-JPM2T9r19ALk2iymtzHj-ew30hMJkyxC-jW7x_iEj1sza-kbL4ARuR9mg
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Chip+scale+package+and+related+methods&rft.inventor=Su+Bingzhi&rft.inventor=Gochnour+Derek&rft.inventor=Kinsman+Larry&rft.date=2017-09-05&rft.externalDBID=B1&rft.externalDocID=US9754983B1