Semiconductor apparatus, processor system, and control method for deallocating and allocating an address range corresponding to a memory between different processors of the processor system
A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the fi...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
11.04.2017
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor. |
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| AbstractList | A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor. |
| Author | Tsuda Tetsuji Ito Yoshiyuki |
| Author_xml | – fullname: Ito Yoshiyuki – fullname: Tsuda Tetsuji |
| BookMark | eNqNTstKQ0EMvQtd-Og_5AMq-CiVblsU99V1iTNn2gv3JkMmRfpx_ptpEUTcuAon53nZnYkKLrrPNcY-qeR9cjXiWtnY921K1TShtXi2Q3OMU2LJFFI3HWiE7zRTCTqDh0ETey_bk-YXJM7ZIoeMZYvwW6AahUfalTiiRrUDvcM_AKHclwKD-M-CRlrId_iz6bo7Lzw0TL7vVUfPT6-rlxtU3UQNJwh887ZezO8Ws9vH5f3DPyRfrXZjKA |
| ContentType | Patent |
| DBID | EVB |
| DatabaseName | esp@cenet |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Medicine Chemistry Sciences Physics |
| ExternalDocumentID | US9619407B2 |
| GroupedDBID | EVB |
| ID | FETCH-epo_espacenet_US9619407B23 |
| IEDL.DBID | EVB |
| IngestDate | Fri Jul 19 16:52:12 EDT 2024 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-epo_espacenet_US9619407B23 |
| Notes | Application Number: US201514593091 |
| OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170411&DB=EPODOC&CC=US&NR=9619407B2 |
| ParticipantIDs | epo_espacenet_US9619407B2 |
| PublicationCentury | 2000 |
| PublicationDate | 20170411 |
| PublicationDateYYYYMMDD | 2017-04-11 |
| PublicationDate_xml | – month: 04 year: 2017 text: 20170411 day: 11 |
| PublicationDecade | 2010 |
| PublicationYear | 2017 |
| RelatedCompanies | Renesas Electronics Corporation |
| RelatedCompanies_xml | – name: Renesas Electronics Corporation |
| Score | 3.0819292 |
| Snippet | A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller... |
| SourceID | epo |
| SourceType | Open Access Repository |
| SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| Title | Semiconductor apparatus, processor system, and control method for deallocating and allocating an address range corresponding to a memory between different processors of the processor system |
| URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170411&DB=EPODOC&locale=&CC=US&NR=9619407B2 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT8JAEJ4QfN4UNeIrczCcaKTQ56ExoYUQEx4RMNxIS7eGg92mLTH-OP-bs0sBjdFjZ9vNdrYzO9P5ZgbgXgvoO7KZoTDD8hUtCHTFagaqYka6ai5ozJJJYv2B0ZtqTzN9VoLlJhdG1gl9l8URSaIWJO-51NfJ7ieWJ7GV2UOwJBJ_7E4cr1Z4x6rZ0Eh2vbbTGQ29oVtzXWc6rg2eHVt46w2zTdp6j6xoUwhD56UtklKS7ydK9wT2RzRZnJ9CicUVOHI3jdcqcNgv4t0VOJAAzUVGxEIIszP4HAtAO49FpVaeop_I8t2rrI7JGvVPxHWB5jr6cYgFGh3XzaKRrFQMmYi3ixeNX-U9Py6RtJHwwjEVmQf0vGjgkXCZ_4I5R5-meuPpBxYgL9x0Wcl3K8iQR0jG5a81nQN2OxO3pxBH5lvuz6fjLe9aF1COecwuAcnr8a1WZEe6YWutkIwG1mShrYa-Ghh-uKhC9c9prv4Zu4ZjsY0iXqOqN1DO0xW7pWM_D-7khn0Bmrq4qw |
| link.rule.ids | 230,309,783,888,25576,76876 |
| linkProvider | European Patent Office |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT8JAEN4QfOBNUSM-52A40Uihz0NjQgtB5RUBw430sTUc7DZtifHH-d-cXQpojB472262s53pzM43M4TcKh5-RybVJKoZrqR4nioZDU-W9FCVdR_HDJEk1h9o3anyOFNnBbJY58KIOqHvojgiSpSP8p4JfR1vD7Ecga1M77wFkth9Z2I51dw7lvW6grLrtKz2aOgM7aptW9NxdfBsmdxbr-st1NY7aGHrXBjaLy2elBJ__6N0DsnuCCeLsiNSoFGZlOx147Uy2e_n8e4y2RMATT9FYi6E6TH5HHNAO4t4pVaWgBuL8t3LtAbxCvWPxFWB5hq4UQA5Gh1WzaIBrVQIKI-38xeNXsU9Py4BtRH3wiHhmQf4PG_gETOR_wIZAxenemPJB-QgL1h3Wcm2K0iBhYDG5a81nRDotCd2V0KOzDfcn0_HG941T0kxYhE9I4Bej2s0QzNUNVNpBmg00AYNTDlwZU9zA79CKn9Oc_7P2A0pdSf93rz3MHi6IAd8S3nsRpYvSTFLlvQKTYDMuxab9wV0DLue |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Semiconductor+apparatus%2C+processor+system%2C+and+control+method+for+deallocating+and+allocating+an+address+range+corresponding+to+a+memory+between+different+processors+of+the+processor+system&rft.inventor=Ito+Yoshiyuki&rft.inventor=Tsuda+Tetsuji&rft.date=2017-04-11&rft.externalDBID=B2&rft.externalDocID=US9619407B2 |