Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory

• Main Authors: Dong Yingda, Pang Liang
• Format: Patent
• Language: English
• Published: 02.08.2016
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Fabrication techniques for a three-dimensional stack memory device remove the charge-trapping material from the select gate transistors and the dummy memory cells to avoid unintentional programming which increases the threshold voltage. In one approach, a stack is formed with a different sacrificial material for the a) control gate layers of the select gate transistors and the dummy memory cells and the b) control gate layers of the data memory cells. A slit is formed to allow etchants to be introduced to selectively remove the sacrificial material and then the charge-trapping material for the select gate transistors and dummy memory cells. Subsequently, an etchant is introduced to remove the sacrificial material but not the charge-trapping material for the data memory cells. In other approaches, a protective layer is provided partway in the slit, or the slit is etched in two steps, and a common sacrificial material can be used.