Method and system for wafer level testing of semiconductor chips
A system and method for wafer level testing of semiconductor chips are provided. In one embodiment, the system comprises a plurality of semiconductor chips disposed in a wafer, each semiconductor chip having at least one port for receiving test data and at least one connection disposed in a kerf reg...
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Format | Patent |
Language | English |
Published |
05.04.2016
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Subjects | |
Online Access | Get full text |
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Abstract | A system and method for wafer level testing of semiconductor chips are provided. In one embodiment, the system comprises a plurality of semiconductor chips disposed in a wafer, each semiconductor chip having at least one port for receiving test data and at least one connection disposed in a kerf region of the wafer between at least one port of a first semiconductor chip and at least one port of at least one second semiconductor chip in the plurality of semiconductor chips, wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the at least one connection. Additionally, the plurality of semiconductor chips may comprise at least one core logic configured to pass the test data to the at least one second semiconductor chip via the at least one connection. |
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AbstractList | A system and method for wafer level testing of semiconductor chips are provided. In one embodiment, the system comprises a plurality of semiconductor chips disposed in a wafer, each semiconductor chip having at least one port for receiving test data and at least one connection disposed in a kerf region of the wafer between at least one port of a first semiconductor chip and at least one port of at least one second semiconductor chip in the plurality of semiconductor chips, wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the at least one connection. Additionally, the plurality of semiconductor chips may comprise at least one core logic configured to pass the test data to the at least one second semiconductor chip via the at least one connection. |
Author | ZHAOJUN SHAO |
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Notes | Application Number: US20100837596 |
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RelatedCompanies | ZHAOJUN SHAO INFINEON TECHNOLOGIES AG |
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Snippet | A system and method for wafer level testing of semiconductor chips are provided. In one embodiment, the system comprises a plurality of semiconductor chips... |
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SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
Title | Method and system for wafer level testing of semiconductor chips |
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