Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures

• Main Authors: TRAN-QUINN THUY L, GRAVES-ABE TROY L, LIU JOYCE C, COLLINS CHRISTOPHER N, PFEIFFER GERD, FAROOQ MUKTA G
• Format: Patent
• Language: English
• Published: 02.02.2016
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).