Computing device with asynchronous auxiliary execution unit
A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary e...
Saved in:
Main Authors | , , , |
---|---|
Format | Patent |
Language | English |
Published |
01.12.2015
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order. |
---|---|
Bibliography: | Application Number: US20100882434 |