Multi-frequency clock skew control for inter-chip communication in synchronous digital systems

• Main Authors: DOBBS CARL S, TROCINO MICHAEL R, SCHREPPEL CHRISTOPHER L, FAULKNER KENNETH R
• Format: Patent
• Language: English
• Published: 06.10.2015
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; CALCULATING; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; PHYSICS; PULSE TECHNIQUE; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

Embodiments are disclosed of an apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal dependent on the clock reference signal. A clock distribution tree and phase-locked loop may be used to minimize internal clock skew at I/O circuitry at the chip perimeter. Each chip may also generate an internal synchronizing signal that is phase-aligned to the received clock reference signal. Each chip may use its respective synchronizing signal to synchronize multiple clock dividers that provide software-selectable adjusted-frequency clock signals to the I/O cells of the chip. In this way, the adjusted-frequency clock signals of the multiple chips are edge-aligned to the low-skew internal clock signals, and phase-aligned to the common clock reference signal, allowing the I/O cells of the multiple chips to perform synchronous communication at multiple rates with low clock skew.