Dynamic and idle power reduction sequence using recombinant clock and power gating
Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other emb...
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Main Authors | , , , , |
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Format | Patent |
Language | English |
Published |
15.07.2014
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Subjects | |
Online Access | Get full text |
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Summary: | Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed. |
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Bibliography: | Application Number: US20100978452 |