TFT array substrate, and liquid crystal display panel
An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material...
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Format | Patent |
Language | English |
Published |
15.07.2014
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Abstract | An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view. |
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AbstractList | An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view. |
Author | OGASAWARA ISAO TANAKA SHINYA YOSHIDA MASAHIRO HORIUCHI SATOSHI YAMADA TAKAHARU KIKUCHI TETSUO |
Author_xml | – fullname: KIKUCHI TETSUO – fullname: YAMADA TAKAHARU – fullname: YOSHIDA MASAHIRO – fullname: TANAKA SHINYA – fullname: OGASAWARA ISAO – fullname: HORIUCHI SATOSHI |
BookMark | eNrjYmDJy89L5WQwDXELUUgsKkqsVCguTSouKUosSdVRSMxLUcjJLCzNTFFILqosLknMUUjJLC7IAaoqSMxLzeFhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwRbmFgbGhoZORsZEKAEA4uwuXQ |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences Physics |
ExternalDocumentID | US8780311B2 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US8780311B23 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 16:52:23 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US8780311B23 |
Notes | Application Number: US200913138396 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140715&DB=EPODOC&CC=US&NR=8780311B2 |
ParticipantIDs | epo_espacenet_US8780311B2 |
PublicationCentury | 2000 |
PublicationDate | 20140715 |
PublicationDateYYYYMMDD | 2014-07-15 |
PublicationDate_xml | – month: 07 year: 2014 text: 20140715 day: 15 |
PublicationDecade | 2010 |
PublicationYear | 2014 |
RelatedCompanies | SHARP KABUSHIKI KAISHA OGASAWARA ISAO TANAKA SHINYA YOSHIDA MASAHIRO HORIUCHI SATOSHI YAMADA TAKAHARU KIKUCHI TETSUO |
RelatedCompanies_xml | – name: TANAKA SHINYA – name: KIKUCHI TETSUO – name: SHARP KABUSHIKI KAISHA – name: YOSHIDA MASAHIRO – name: OGASAWARA ISAO – name: HORIUCHI SATOSHI – name: YAMADA TAKAHARU |
Score | 2.9427636 |
Snippet | An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FREQUENCY-CHANGING NON-LINEAR OPTICS OPTICAL ANALOGUE/DIGITAL CONVERTERS OPTICAL LOGIC ELEMENTS OPTICS PHYSICS SEMICONDUCTOR DEVICES TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF |
Title | TFT array substrate, and liquid crystal display panel |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140715&DB=EPODOC&locale=&CC=US&NR=8780311B2 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1La8MwDBale962bGPdCx9GTgtrl7hJD2XQpKEM-mBNR2-liRwIhLRLUkb__WSTdrtsV9kYW_iTZVn6DPDYtGPRRN4xYsHbhiytNBxE03BMx7bQtMULyjjkcNQezKy3OZ_XINnVwiie0C9FjkiIigjvpbLX658glqdyK4vnMCHR6tUPup5e3Y5b8nrCda_X7U_G3tjVXbc7m-qjd7LqDm3fVo-s9QF50bYEQ_-jJ4tS1r9PFP8MDic0WFaeQ01kGpy4u4_XNDgeVu_dGhypBM2oIGEFwuICeOAHbJnnyy0rCPaKXvaJLTNkafK5SZBF-ZZ8vpRhUqxT6kWAF-klML8fuAODZrLYr3oxm-7nbF5BPVtl4hpYTBhEWwiOsWU1heSWCUPsOBE5ySHG2IDGn8Pc_NN2C6dSfTJq2eJ3UC_zjbin47YMH5SivgFMwISK |
link.rule.ids | 230,309,783,888,25576,76876 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_G_JhvOhXnZx6kTxY326zdwxDarkzdF66VvY21SaFQutl2yP57L6GbvujrJYTkyO9yudz9AnDfNCLeZLSjRpy2VVFaqZqMaaqpmYbONIM_MRGHHI7afV9_ndFZBeJtLYzkCf2S5IiIqBDxXkh7vfoJYjkytzJ_DGIULZ9dr-so5e24Ja4nVHGsbm8ydsa2Yttdf6qM3tGqm7h9WxZa6z30sA0Bht6HJYpSVr9PFPcY9ic4WFqcQIWndajZ24_X6nA4LN-763AgEzTDHIUlCPNToJ7rkUWWLTYkR9hLetkHskgZSeLPdcxImG3Q50sIi_NVgr0Q8Dw5A-L2PLuv4kzmu1XP_eluzto5VNNlyi-ARIhBZnBOWaTrTS64ZYKAdcwQneSARawBjT-Hufyn7Q5qfW84mA9eRm9XcCRUKSKYLXoN1SJb8xs8eovgVirtG69hh30 |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=TFT+array+substrate%2C+and+liquid+crystal+display+panel&rft.inventor=KIKUCHI+TETSUO&rft.inventor=YAMADA+TAKAHARU&rft.inventor=YOSHIDA+MASAHIRO&rft.inventor=TANAKA+SHINYA&rft.inventor=OGASAWARA+ISAO&rft.inventor=HORIUCHI+SATOSHI&rft.date=2014-07-15&rft.externalDBID=B2&rft.externalDocID=US8780311B2 |