Methods of fabricating a semiconductor IC having a hardened shallow trench isolation (STI)
Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed p...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
29.10.2013
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Subjects | |
Online Access | Get full text |
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