Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includ...

Full description

Saved in:
Bibliographic Details
Main Authors UEHARA TADAO, NISHIHARA KENJI, HARUKI TOHRU, TOCHISHITA SHOUJI, ISHIBUSHI KIYOTAKA
Format Patent
LanguageEnglish
Published 23.04.2013
Subjects
Online AccessGet full text

Cover

Loading…
Abstract A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps of coating the entire main surface of the semiconductor wafer with a positive photosensitive resist, defining an additional exposure area in the blank area, conducting a first exposure process on the peripheral area and the additional exposure area, conducting a second exposure process on the device chip area, removing resist remaining on predetermined areas of the device chip area, the peripheral area and the blank area after conducting the first and second exposure processes for forming a resist pattern, and dry-etching the main surface of the semiconductor wafer by using the resist pattern as a mask.
AbstractList A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps of coating the entire main surface of the semiconductor wafer with a positive photosensitive resist, defining an additional exposure area in the blank area, conducting a first exposure process on the peripheral area and the additional exposure area, conducting a second exposure process on the device chip area, removing resist remaining on predetermined areas of the device chip area, the peripheral area and the blank area after conducting the first and second exposure processes for forming a resist pattern, and dry-etching the main surface of the semiconductor wafer by using the resist pattern as a mask.
Author UEHARA TADAO
ISHIBUSHI KIYOTAKA
TOCHISHITA SHOUJI
NISHIHARA KENJI
HARUKI TOHRU
Author_xml – fullname: UEHARA TADAO
– fullname: NISHIHARA KENJI
– fullname: HARUKI TOHRU
– fullname: TOCHISHITA SHOUJI
– fullname: ISHIBUSHI KIYOTAKA
BookMark eNrjYmDJy89L5WTQ8U0tychPUchPU8hNzCtNS0wuKS3KzEtXKE7NzUzOz0spTS7JL1JISS3LTE7lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocEWJkZmxoamTkbGRCgBAFy-K7Y
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US8426315B2
GroupedDBID EVB
ID FETCH-epo_espacenet_US8426315B23
IEDL.DBID EVB
IngestDate Fri Jul 19 13:04:55 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US8426315B23
Notes Application Number: US20060525658
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130423&DB=EPODOC&CC=US&NR=8426315B2
ParticipantIDs epo_espacenet_US8426315B2
PublicationCentury 2000
PublicationDate 20130423
PublicationDateYYYYMMDD 2013-04-23
PublicationDate_xml – month: 04
  year: 2013
  text: 20130423
  day: 23
PublicationDecade 2010
PublicationYear 2013
RelatedCompanies RICOH COMPANY, LTD
UEHARA TADAO
ISHIBUSHI KIYOTAKA
TOCHISHITA SHOUJI
NISHIHARA KENJI
HARUKI TOHRU
RelatedCompanies_xml – name: RICOH COMPANY, LTD
– name: ISHIBUSHI KIYOTAKA
– name: TOCHISHITA SHOUJI
– name: HARUKI TOHRU
– name: NISHIHARA KENJI
– name: UEHARA TADAO
Score 2.8786054
Snippet A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Method of manufacturing semiconductor device
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130423&DB=EPODOC&locale=&CC=US&NR=8426315B2
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KFfWmVbG-yEFyMpjH5nUIQl4UIW2xjfRWtvuAHkxKk-Lfd3dJqxe9Lbsw-4CZ2dmd7xuAJxRwjE2GDMaxayBCiREQhxnU8W3MhT-mTD4NFGNvVKK3hbvowXqPhVE8oV-KHFFoFBH63ip7vfl5xEpVbmXzslqLrvo1n0ep3kXHlgzOHT2No2w6SSeJniRROdPH71EgicktNxbW-kjeoiXNfvYRS1DK5rdHyc_heCqEVe0F9Fg1gNNkX3htACdF998tmp3qNZfwXKhaz1rNtU9c7SQgQSEMtUamt9eV5G2ttxplUvWvQMuzeTIyxLTLwxaX5eywQOca-iLyZzegmYz4LvE9M8A2wqGFw5BzZBHqe5y41BzC8E8xt_-M3cGZrao6IMN27qHfbnfsQfjWdvWoTuUbd2l_pg
link.rule.ids 230,309,786,891,25594,76906
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV07T8MwED5VBVE2KCDKMwPKREQezqNDhJSkUYAmrWiLulWuY0sdSKomFX8f20oLC2yWLZ0f0t357Pu-A3hAHsNYp0ijDNsaIjnRPGJRLbdcEzPuj3MqngbSzElm6HVuz1uw2mFhJE_olyRH5BpFuL7X0l6vfx6xIplbWT0tV7yrfI6nfqQ20bEhgnNLjQJ_MB5Fo1ANQ382UbN33xPE5IYdcGt94ApyXnFz-ggEKGX926PEJ3A45sKK-hRatOhCJ9wVXuvCUdr8d_Nmo3rVGTymstazUjLlExdbAUiQCEOlEuntZSF4W8uNklOh-uegxINpmGh82sV-i4vZZL9A6wLaPPKnl6DolLg2cR3dwybCfQP3-4whg-Suw4id6z3o_Snm6p-xe-gk03S4GL5kb9dwbMoKD0gzrRto15stveV-tl7eyRP6BpfugpM
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Method+of+manufacturing+semiconductor+device&rft.inventor=UEHARA+TADAO&rft.inventor=NISHIHARA+KENJI&rft.inventor=HARUKI+TOHRU&rft.inventor=TOCHISHITA+SHOUJI&rft.inventor=ISHIBUSHI+KIYOTAKA&rft.date=2013-04-23&rft.externalDBID=B2&rft.externalDocID=US8426315B2