SRAM bit cell

A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to...

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Bibliographic Details
Main Authors WANG PING, LIN JIHI-YU, CHOU SHAO-YU, LIAO HUNG-JEN, CHEN YEN-HUEI
Format Patent
LanguageEnglish
Published 29.01.2013
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.
Bibliography:Application Number: US201113015773